DFT Engineer Intern
Ambarella · US Headquarters
- Company
- Ambarella
- Work style
- Unknown
- Employment
- Full Time
- Location
- US Headquarters
- Published
- 2026-08-27
- Source checked
- 2026-10-28
- Listing source
- Workday public career sites
About this role
AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Position Responsibilities: Logic Design to support DFT features Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC Verification of DFT Logic and analysis of fault coverage Timing analysis for DFT Modes Minimum Requirements: MSEE in Electrical / Computer Engineering Knowledge of DFT fundamentals Knowledge of Logic design & Static timing analysis Knowledge of Verilog and any scripting language Knowledge of AI assisted programming
Check the original listing
Confirm current requirements and eligibility with the source before applying.